MEMS Packaging – In the past decades, many advances have been made in the fabrication of miniaturized mechanical structures called MEMS. Yet the application of this technology is hampered by the lack of production-worthy, MEMS-compatible packages. MEMS packages must not only protect the often-fragile mechanical structures and provide the interface to the next level in the packaging hierarchy, but they must also be fabricated in a cost effective manner to allow for affordable mass-produced circuits. Since several thousand RF switches are simultaneously fabricated on a single substrate, a cost effective packaging process should perform most of the packaging steps at a wafer level, before separation into discrete circuits.
There are several wafer-level packaging (WLP) techniques widely used with silicon micromachining; these include fusion bonding, anodic bonding, eutectic bonding, thermal compression bonding, and glass-frit bonding. While some of these packaging techniques have been demonstrated with non-RF MEMS circuits, their use for RF MEMS is limited. An ideal bonding technique should yield a hermetic seal that has a dielectric constant equal to the substrate, can be processed at low temperatures, and can tolerate a large degree of non-planarity/roughness.
Wafer-level packaging enables the whole MEMS wafer to be packaged at once, while in the controlled environment of the cleanroom.
There are several wafer-level packaging (WLP) techniques widely used with silicon micromachining; these include fusion bonding, anodic bonding, eutectic bonding, thermal compression bonding, and glass-frit bonding. While some of these packaging techniques have been demonstrated with non-RF MEMS circuits, their use for RF MEMS is limited. An ideal bonding technique should yield a hermetic seal that has a dielectric constant equal to the substrate, can be processed at low temperatures, and can tolerate a large degree of non-planarity/roughness.
Wafer-level packaging enables the whole MEMS wafer to be packaged at once, while in the controlled environment of the cleanroom.
MEMS Wafer Fab Wafer Scale Bonding Device Testing Singulation
One drawback of most wafer-level packaging techniques is the requirement for a seal ring. The inclusion of a seal ring and the appropriate bonding pads outside the ring significantly increases the area of an RF MEMS circuit. In such a circuit, there are four areas that need to be considered: 1) the RF MEMS circuit, 2) the seal ring, 3) the interconnect area, and 4) the saw kerf. The regions required for the seal ring, interconnect area, and the saw kerf increase the final size of the RF circuit, thereby reducing the available number of circuits per wafer. The glass-frit WLP technique typically requires a seal ring and interconnects area of 0.3-0.7 mm per side. The difference in realized circuits per wafer is substantial. For example, assuming a 1 x 2 mm RF MEMS phase shifter and a 150 mm wafer (with a 5 mm exclusion zone and 150 µm saw kerf), there are 2152 potential phase shifter die per wafer for glass-frit WLP. The same circuit without a 0.5 mm seal ring/interconnect area all around the die yields 6000 potential circuits per wafer. This produces 2.8x more phase shifters for the same wafer area! Eliminating the seal ring area greatly increases the number of available circuits per wafer, which significantly reduces the cost per circuit
Advantages – An innovative approach to packaging currently being developed at MEMtronics is called wafer-level microencapsulation (WLµE). Microencapsulation is designed to be completely compatible with RF MEMS switch fabrication This wafer-level packaging scheme eliminates the seal ring to give the potential payoff of much smaller, lower cost circuits. Instead of bonding a separate glass wafer to the RF MEMS wafer, individual micropackages are constructed on top of each RF switch using the same MEMS processes used to construct the switch. This microencapsulation process yields a protective, low-loss, package with RF friendly interconnects. These packaging processes require only moderate process temperatures (200oC – 250oC) and tolerate both non-planarity and roughness. Utilizing standard semiconductor and MEMS fabrication processes for microencapsulation creates a cost-efficient and effective packaging alternative. MEMtronics' innovative micro-encapsulation process accounts for only 28% of total packaged switch cost compared to many conventional strategies that account for 70-80% of total cost.
Some of the advantages of this unique microencapsulation technique are:
• No seal ring
• Extremely small volume cavity
• No requirement for a package lid
• No double-wafer alignment required
• Requires only standard MEMS processing
• Substantial increase in the number of circuits per wafer
• Extremely low insertion loss
• No added parasitics
• Packaged circuits are thinner/lighter than any other packaging technique
• No seal ring
• Extremely small volume cavity
• No requirement for a package lid
• No double-wafer alignment required
• Requires only standard MEMS processing
• Substantial increase in the number of circuits per wafer
• Extremely low insertion loss
• No added parasitics
• Packaged circuits are thinner/lighter than any other packaging technique
Microencapsulation of individual switches on a die increases the number of available die per wafer.
Microencapsulation Construction – After the switches are constructed, the process steps to produce a wafer-level micro-encapsulation of RF MEMS switches are as follows:
1. Use a sacrificial layer to form a temporary encapsulation above and around the unreleased membrane.
2. Deposit an insulator to form a structural shell.
3. Pattern and etch the insulator to form a cage-like structure on top of the sacrificial layer.
4. Plasma ash the photoresist to create a microcavity structure and also release the membrane. Once the sacrificial layer is removed, there is in place a cage-like structure, separated by a gap, over the released membrane.
5. Apply a liquid encapsulant, such as benzocylcobutene (BCB), to the entire wafer. The surface tension of the encapsulant ensures the cage structure is covered without wicking through the holes to encroach onto the switch.
6. Cure the encapsulant to create a closed seal over the microcavity. This step can go up to 250°C since all sacrificial layers have been removed.
7. Apply optional sealant overcoats (such as parylene) for additional protection.
Results – MEMtronics has developed the new technique called wafer-level micro-encapsulation to effectively package RF MEMS switches. This technology was designed to be completely compatible with high-performance RF MEMS capacitive switch fabrication. The packages exhibit extremely low package-added insertion loss of 0.04 dB at 35 GHz, and < .10 dB for frequencies up to 110 GHz. Substantial lifetime characterization of these packages is an on-going activity, but initial results are promising. Preliminary accelerated lifetime data show using BCB spin-on encapsulation indicates an RF MEMS lifetime of ~55 years at room conditions. Additional sealant layers have shown very good promise by increasing the lifetime by an order of magnitude (>600 years). The compatibility of the package with MEMS switch processing, the extremely low loss and RF parasitics, and the potential for near-hermetic encapsulation makes this technology a promising solution for packaging and protecting RF MEMS switches. MEMtronics' innovative approach to packaging ensures protection for RF MEMS devices under harsh conditions, while providing a reliable, cost effective product.
EVER TENEPPE
17767425
MATERIA: EES
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