lunes, 26 de julio de 2010

Tipos de antenas de radar

Un phased array consiste en una matriz (array) de elementos radiantes. La fase de la señal que alimenta cada uno de estos está controlada de tal manera que la radiación del conjunto sea muy directiva. Es decir, se juega con las fases de las señales para que se cancelen en las direcciones no deseadas y se interfieran constructivamente en las direcciones de interés.

Un phased array ("agrupación de antenas controladas por fase") es un conjunto de antenas array) en el cual las fases relativas de las señales con que se alimenta cada antena se varían intencionadamente con objeto de alterar el diagrama de radiación del conjunto. Lo normal es reforzar la radiación en una dirección concreta y suprimirla en direcciones indeseadas.

Esta tecnología fue desarrollada originalmente por el futuro Premio Nobel Luis Walter Álvarez durante la Segunda Guerra Mundial, para funcionar en radares de respuesta rápida destinados a aplicaciones de Ground-Controlled Approach (GCA), es decir, de ayuda al aterrizaje de aeronaves. Más tarde se adaptó para usos en radioastronomía, valiéndole el Premio Nobel de Física a Anthony Hewish y Martin Ryle, tras desarrollar phased arrays de gran tamaño en la Universidad de Cambridge. El diseño se usa por tanto en radar y es de uso habitual en antenas de radio interferométricas.

Si todos los elementos del array están contenidos en el mismo plano y la señal con que se alimentan es de la misma fase, entonces se estará reforzando la dirección perpendicular a ese plano. Si se altera la fase relativa de las señales se podrá "mover" el haz (en realidad lo que se está haciendo es cambiar la dirección en la cual las interferencias son constructivas). Se consigue de este modo hacer barridos sin necesidad de movimiento físico, con la ventaja añadida de que se pueden escanear ángulos del orden de miles de grados por segundo. Esto permite utilizar la antena para compaginar simultáneamente funciones de detección y de seguimiento muchos blancos individuales. Apagando y encendiendo algunos de los elementos radiantes se puede variar el haz de radiación, ensanchándolo para mejorar las funciones de búsqueda o estrechándolo para hacer un seguimiento preciso de un objetivo. El punto débil de los phased arrays es la imposibilidad de dirigirlo correctamente en ángulos cercanos al plano en el que están los elementos radiantes. Para hacer una cobertura de 360º se suelen disponer 3 arrays en las paredes de una superficie piramidal.

En radioastronomía también se emplean los phased arrays para, por medio de técnicas de apertura sintética, obtener haces de radiación muy estrechos. La apertura sintética se usa tambié en radares de aviones.

El diagrama de radiación del array se obtiene como la interferencia de los campos radiados por cada una de las antenas. En recepción la señal recibida es una combinación lineal de las señales que capta cada antena. El diagrama de radiación total viene dado por el diagrama de radiación conjunto y el diagrama de radiación del elemento aislado.

En el diseño de arrays intervienen muchos parámetros : número de elementos, disposición física de los elementos, amplitud de la corriente de alimentación, fase relativa de la alimentación y tipo de antena elemental utilizada.

Configurando estos parámetros se pueden mejorar las características de radiación del diagrama de radiación individual : mejorar la directividad, mejorar la relación de lóbulo principal a secundario, conformar el diagrama para cubrir la zona de interés y tener la posibilidad de controlar electrónicamente el apuntamiento del haz principal.

El uso de los phased arrays se remonta a la Segunda Guerra Mundial, pero las limitaciones de la electrónica hacían que fueran poco precisos. Su aplicación original era la defensa anti-misiles. En la actualidad son parte imprescindible del sistema AEGIS y el sistema balístico MIM-104 Patriot. Su uso se va extendiendo debido a la fiabilidad derivada del hecho de que no tienen partes móviles. Casi todos los radares militares modernos se basan en phased arrays, relegando los sistemas basados en antenas rotatorias a aplicaciones donde el costo es un factor determinante (tráfico aéreo, meteorología,...) Su uso está también extendido en aeronaves militares debido a su capacidad de seguir múltiples objetivos. El primer avión en usar uno fue el B-1B Lancer. El primer caza, el MiG-31 ruso. El sistema radar de dicho avión está considerado como el más potente de entre todos los cazas.

En radioastronomía también se emplean los phased arrays para, por medio de técnicas de apertura sintética, obtener haces de radiación muy estrechos. La apertura sintética se usa también en radares de aviones.

Jorge Polentino
19769972
CRF

Adaptive Antenna Array for Satellite

Antennas are classified as either single element or array antennas (multi element). Single element antennas are either omni directional or directional. Omni directional antennas have equal gain in all directions and are also known as isotropic antennas. Directional antennas have maximum gain in desired directions and less in others.

Antenna array is an arrangement of many individual antennas which are placed in space and phase such that the contribution of individual antennas add in one desired direction and cancel in other directions. The antenna arrays are used to generate electronically steer able antenna patterns. The adaptive antenna array adjusts their pattern automatically to signal environment to reduce interference. The desired signal reception is maintained by steering the main beam. Spacing between array elements is an important factor in designing antenna arrays.

Antenna array may be phased array or adaptive array. A phased array antenna system is an array of omni directional or directional element antennas in which the signal induced on the antennas are combined to form an array output. Such an antenna system controls the direction where maximum gain appears by adjusting the phase difference between different antenna elements. An adaptive antenna array combines the outputs of antenna elements but controls the directional gain of the antenna by adjusting both phase and amplitude of the signal at each individual element. Satellite antenna consists of a parabolic reflector with horn antenna at its focus. Basically horn is used as feed for parabolic reflector. Usually Horn is placed at the focus of paraboloid.. The horn antenna have desirable property that it effects a smooth transition from medium like waveguide which supports finite number of propagating modes to a medium like free space which supports a infinite number of modes.In most satellite communication systems, interference remains a problem for reliable reception of signals. Adaptive antenna array for satellite communication systems is better than omni directional antenna that radiate in all directions. Hence for this we use adaptive antenna array that automatically steer the beam in the direction of desired signal i.e. signal of interest (SOI). An antenna array has same directional performance as that of larger antenna . And radiation pattern is an important property of antenna. The overall radiation pattern of an antenna array is obtained by the radiation pattern of the individual elements, their positions, orientation in space and relative phase and amplitudes of the feeding currents to the elements.

Adaptive antenna arrays have ability to adapt changing environment conditions to maximize signal strength of signal of interest (SOI) [4]. In this paper MATLAB software has been used to obtain array voltage patterns for different values of number of elements in antenna array i.e. M and angle of beam steering i.e. x by using LMS algorithm.

ARRAY DESIGN ARCHITECTURE
The overall array pattern can be steered in direction of desired user without physically moving any of individual elements by varying amplitude and phase of individual elements output before combining . The overall radiation pattern of an array is obtained by radiation pattern of individual elements, their positions, orientation in space and the relative amplitude and phase of feeding currents to the elements .Figure '1'shows adaptive antenna array whose architecture is based on LMS algorithm .It is shown in the figure that antenna array is a linear array in which centers of antenna elements are placed along straight line. Since the signals incident on all the antenna elements are of different phases due to the difference in distance traveled by the wave between two antenna elements.

The signal present at element one has traveled more distance Dsin( x) than signal present at element two [1].Where D is distance between successive antenna phase centers in the array as shown in figure 1. Therefore phase of element one will lag behind that of element two by βDsin(x).
Where

β (Phase propagation factor)= 2π /λ

Here λ =wavelength of received signal. In this figure1 the incident waves are defined as s(t) . We will assume that the receiver will down convert the signal to its Intermediate Frequency (IF) while the Analog-to-Digital converter (A/ D) will down convert the signal to its base band equivalent [4]. As they reach the antenna elements, the waves are converted to electrical sinals x(t) . From Figure1, we define the input signals as ( ), ( ),......... ( ) 1 2 x t x t x t n . These signals are then multiplied by the input weights n w ,w ,........w 1 2 . Then output signal y(t) is the weighted sum of the input signals




Where
n : Number of the weights. The error signal e(k) in the following figure represents the difference between the summed output, y(k) and the reference signal r(k) . The error processor then computes the required weight adjustment necessary in order to null out the undesired signal. This process is an iterative process and will continue until all the weights in the array converge. Consider a narrow band incident wave as:

S(t) = Aexp(2πf t +φ ) c (2)

Where
A : Amplitude of the signal.
c f : Carrier frequency.
φ : Phase difference between incidents waves at
successive elements. i.e. φ = 2π /λDsin(x)


By taking received signal at element one as the reference, the received signals x (t) i for uniform linear array with element spacing D is represented in matrix form as.




For adaptive beam forming, each element output x (t) i is multiplied with weight i w that modify phase and amplitude relation between the branches and summed to give output y(t).


The overall antenna pattern is continuously modified by adjusting weight vector. For digital communication system, the input signals are in discrete time sampled data form.

Therefore output is:


LMS ALGORITHM
Basic Description

The LMS algorithm was first introduced by Widrow et al and operates with a priori knowledge of the direction of arrival and the spectrum of the signal but with no knowledge of the noise and interference in the channel. This algorithm is useful when the interference contains some pectral correlation with the SOI. Minimization of the MMSE can be accomplished by a gradient-search technique. The particular method that the LMS algorithm uses is known as the steepest decent technique. For this particular technique, the changesin the weight vector are made along the direction of the estimated gradient vector.


Here we can see that the LMS algorithm does not require squaring, averaging or differentiating and hence can be implemented in most practical systems . Its popularity is accredited to the fact that it is simple, easy to compute and efficient. However, the drawback is that the weights for this algorithm take a long time to converge.

B. The Convergence Rate of the LMS Algorithm The parameter μ is the gain constant that regulates the speed and stability of adaptation. It determines the convergence rate. This gain factor is bounded by the limits

0 < μ <>
Where max λ : Largest Eigen value of the input correlation matrix. RESULTS Figures 2, 3, 4 show array voltage patterns for different values of number of elements in antenna array (M) and angle of beam steering (x) as given in table I.

The magnitude of the initial pattern is determined by the initial (arbitrary) choice of weights, w whereas the magnitude of the final pattern is determined by the strength of the desired signal, the direction and strength of the interfering signal and the noise in the system.

It is observed in figure 2, maximum gain occurs at an angle of 30° as angle of beam steering is fixed at 30°. The figure 3 shows that main beam is at an angle of 45° because signal is received by the receiver at this angle In figure 4, the maximum gain occurs at an angle of 60° as angle of beam steering is fixed at 60°


Jorge Polentino

CRF



http://www.iaeng.org/publication/IMECS2008/IMECS2008_pp1491-1494.pdf

Reconfigurable Patch-Slot Reflectarray Elements using RF MEMS Switches:

A microstrip reflectarray is a low-profile, inexpensive antenna which combines some of the best features of reflectors and microstrip arrays [1, 2]. Reflectarray surface which consists of isolated radiating elements is illuminated by a feed antenna. These radiating elements (patches or dipoles) are pre-designed with a particular phase delay such that the illuminating electric field from the feed will be re-radiated and scattered from these elements to form a prescribed phase front in front of the aperture. The reflectarray concept is based on the scattering properties of these radiating elements. There are several different ways to control the phase of an individual element. Some of them are - microstrip patches with the same shape and size loaded with variable length stubs [1], variable size dipoles or microstrip patches, microstrip patches with same shape but different sizes [3], identical microstrip patches on the top layer loaded with variable length slots on the ground plane [4].

The concept of reconfigurable reflectarray element is beneficial for reflectarray design as it allows for dynamic phase control of a single radiating element. Each radiating element can have a similar physical structure and the desired phase response can be achieved by electronically manipulating each element. This reconfigurable reflectarray using MEMS switches can be used as a subreflector to compensate for the distortions on the main reflector as shown in Fig. 1. This is a novel concept with future applications. The passive reflectarray can only compensate for static distortions on the main reflector while the reconfigurable reflectarray can compensate for both the static and dynamic distortions. The purpose of this paper is to investigate potential reflectarray elements by taking into consideration the eventual implementation of MEMS technology for this particular application and detailed characterization of one of the potential element designs.

Reflectarray element: Variable slot on the ground plane

Different reflectarray designs were studied for this particular application as shown in Fig. 2. It was decided that the element with variable slot on the ground plane was best suited keeping in mind the MEMS implementation. The detailed characterization of the element involved testing the concept of reconfigurability and measurement of the phase response of a unit cell design. The principle of operation of the reconfigurable microstrip slotloaded patch reflectarray shown in Fig. 3 (a) is as follows. Radiating patch elements of equal sizes are printed on the top layer and a slot of fixed length is cut in the ground plane of each element. RF MEMS switches are implemented on the slot and length of the slot is changed by turning the switches ON/OFF. In absence of the slot, each patch radiates at its resonant frequency. The presence of slots acts as an inductive loading and introduces a phase shift. Thus, the phase of the reflected field from each unit cell of the reflectarray can be changed by determining the location of the RF MEMS switches.

Reflection Phase: Simulation and Measurement Results

Fig. 3 (b) shows the HFSS simulated model of the reflectarray element. Waveguide simulation approach was used in HFSS. Fig. 4 (a) shows the measurement setup. Figs. 4 (b) and (c) show the sample with different effective slot lengths attached to the S-band waveguide. The slot length was fixed and copper strips were used as shorting switches to reduce the effective length of the slot. The frequency (f) of operation was 2GHz (angle of incidence = 43°). The free space wavelength (λ) was 15cm and guided wavelength (λg) was 10.11mm). The unit cell size was 10.9cm x 5.5cm. Substrate with 31 mil thickness and dielectric constant of 2.2 was used. The patch size on the top layer was 4.7cm x 4.7cm (0.47 λg x 0.47 λg). The slot width on the ground plane was fixed to 0.28mm (0.028 λg). The dimensions of the copper strips (switches) were 1.5mm x 5mm. The dimensions of commercially available MEMS switches are around 1.5mm x 1.5mm. The copper strips (switches) used in the present design have the same width (1.5mm). The dimensions of the patch and the slot were chosen such that the patch is in resonance and the slot does not radiate. The only purpose of the slot is to load the patch and change the phase of the reflected field. Fig. 4 shows the comparison between the simulated and measured reflection phase results for the frequency of 2GHz. It can be seen that there is a very good agreement between the measured and simulated results. This verifies the reconfigurability concept for the design. Present efforts are on to integrate the commercially available switches in the present design and measure the reflection phase and also study the losses associated with the present geometry.

Reconfigurable feature offers electronic control of each element which provides for easier implementation of the whole reflectarray system. Several potential reflectarray element designs were investigated with critical importance given to the consideration of MEMS implementation in the final design. The reflectarray element with variable slot on ground plane and fixed patch on top was selected for final characterization. The concept of reconfigurability was tested for this design, unit cell of this reflectarray was fabricated and tested, and reflection phase measurements were performed. Future work includesmplementation of the actual switches models (MEMS) in the simulation, characterization of losses and development of an addressing scheme for the switch
















Jorge Polentino
CRF
196769972

http://www.ee.ucla.edu/~harish/C9-IEEEAP-07.pdf

A MEMS Reconfigurable Matching Network

circuit reconfigurability has received tremendous attention during the past years, especially in the development of wireless communication systems. There has been considerable interest in developing adaptive components which can be electrically tuned for various applications [1], [2]. Microelectromechanical system (MEMS), on the other hand, has been demonstrated to be one of the most promising technologies in developing devices with high performance, low cost, small size and wide tunability. Particularly, it has been seen that RF MEMS switches, both capacitive and metal-to-metal contact provide very low insertion loss, low power consumption and very high linearity in high frequency applications [3], [4]. It is believed that those MEMS devices have enormous potential in achieving circuit reconfigurability due to their superior performance and the fabrication compatibility with existing IC technology [5], [6].

In this letter, a reconfigurable amplifier is designed with a tunable input and output matching network. The matching network is tuned to provide matching at different frequencies for optimum power added efficiency (PAE) and power gain. This tunability is achieved by incorporating shunt MEMS capacitive switches into the matching network. The design issues are discussed and the circuit simulation and measurement results are presented.

Active Device
The transistor used in this design is Agilent ATF-34 143 which is a high dynamic range, low noise PHEMT device packaged in a 4-lead SC-70(SOT-343) surface mount plastic package. The transistor has threshold voltage of 0.95 V and transconductance parameter of 0.24 . Based on the device arameters and the design objective, the biased condition of the transistor is chosen to be V, V and mA. This corresponds to a class AB operation. Fig. 1 shows the block diagram of the amplifier. The input matching and output matching networks provide the transistor with the optimum source and load impedances for the maximum power added efficiency and power gain. A load-pull simulation is carried out in ADS using the available device model to find out the optimum load and source impedances for the maximum power added efficiency under the particular bias condition at 8 dBm input

Reconfigurable Matching Network
It is well known that a double-stub network can provide tunable matching for different impedances. Such a matching network is composed of a fixed length transmission line and two shunt stubs. The procedure of designing a double-stub matching network is described in [7]. For a given stub spacing, d, the range of (the real part of the admittance) that can be matched is given by




where is the imaginary part of the load impedance, is the character admittance and . The equivalent capacitance of the two stubs can then be calculated as

The input and output matching networks are designed following this procedure. Fig. 2 shows the schematics of the two double-stub tuner on a Si substrate. The stubs are implemented with both fixed value MIM capacitors and MEMS capacitive switches. As reported in [8], the implemented MEMS shunt switch behaves as a shunt capacitor between the center conductor of the CPW line and the ground. The capacitance of the switch can be varied to either or by activating the switch. In the input matching network [Fig. 2(a)], the second stub has capacitance of 0.65 pF (provided by MIM capacitor 2) in one configuration and 2.15 pF in the other configuration. Due to the limitation of the down capacitance that a single switch can provide, two MEMS switches are used to provide 1.5 pF when they are pulled down. In the output matching network, both stubs are implemented by one MEMS switch with down-capacitance of 0.28 pF and 0.22 pF, respectively [Fig. 2(b)]. Since the loss introduced by the MEMS switch is quite low [8], the implemented matching network has very low loss even at high frequency range.

FABRICATION PROCESS
The fabrication process starts with a high resistivity Si substrate (approximately 2000 cm) covered with 2000 Si . A lift-off process is applied to define the m finite ground coplanar waveguide (FGCPW) lines, which are made of 200 of Cr and 8000 of Au. 2000 of silicon nitride is then deposited on the wafer with a PECVD process and a RIE process is followed to pattern the nitride layer.Asacrificial layer (SC1827 photoresist by Shipley) of about m is spin coated and patterned to form the anchor points for the switch and the openings for the MIM capacitor. This is followed by a sputtering deposition of m Au film. The Au film is then patterned to form the switch membrane and the top metal layer of the MIM capacitors. The process flow is illustrated in Fig. 3 and SEM pictures of the fabricated switches are shown in Fig. 4. After the circuit is fabricated, the ATF-34 143 transistor is mounted onto the wafer using conductive epoxy adhesive. Microscope pictures of the completed circuit are shown in Fig. 5.

MEASUREMENTS AND DISCUSSION
The RF performance of both input and output matching networks was measured by a 8510C Vector Network Analyzer on an Alessi Probe Station with GGP Picoprobe 150 m pitch coplanar probes. The effects of the probes and the connecting cables were de-embedded by standard TRL calibration. The S-parameters of the matching network are shown in Fig. 6. Fig. 6(a) and (b) shows the response of the input matching network at two design configurations. At the 6 GHz configuration, both switches are pulled down. While at the 8 GHz configuration, both switches are up. Fig. 6(c) and (d)




the S-parameters of the output matching network. In the 6 GHz design configuration, the first switch is up and the second switch is down (see Fig. 2). While at the 8 GHz configuration, is down and is up. Both measured and simulated S-parameters are shown in this figure.

The power gain and PAE of the amplifier were measured by connecting the input port to a HP 83624A Synthesized Sweeper and the output port to a HP 8564E Spectrum Analyzer. To calibrate the test setup, the circuit was replaced with a through line and the loss of the connecting cables and probes were measured. At the bias condition described in Section II and dBm of the amplifier were recorded at the two matching configurations. The power gain and PAE are calculated as
The results are shown in Fig. 7. Simulation results are also given in the figure. The PAE and gain are improved at high frequency when the matching network is switched from configuration 1 (6 GHz design) to configuration 2 (8 GHz design). Table II summarizes the Maximum Available Gain (MAG), simulated PAE, the measured gain and PAE at two peak frequencies.

We have demonstrated a reconfigurable amplifier design with maximum PAE and power gain at 6 GHz and 8 GHz. The adaptive matching networks are implemented with MEMS capacitive switches to provide matching conditions for both input and output at different frequencies. The RF responses of the matching networks at two design configurations are measured as well as the power performance of the amplifier.This technique can be applied to other circuit designs where reconfigurability of the circuit is required.
Jorge Polentino
CRF
http://cobweb.ecn.purdue.edu/~saeedm/J15.pdf

MEMS MICRO-SWITCH ARRAY BASED ON CURRENT LIMITING ENABLED CIRCUIT INTERRUPTING APPARATUS

The present invention comprises a micro-electromechanical system (MEMS) micro-switch array based current limiting enabled circuit interrupting apparatus. The apparatus comprising an over-current protective component, wherein the over-current protective component comprises a switching circuit, wherein the switching circuit comprises a plurality of micro-electromechanical system switching devices. The apparatus also comprises a circuit breaker or switching component, wherein the circuit breaker or switching component is in operable communication with the over-current protective component.
Claims:

1. A MEMS micro-switch array based current limiting enabled circuit interrupting apparatus, the apparatus comprising:an over-current protective component, the over-current protective component comprising:a switching circuit, wherein the switching circuit comprises a plurality of micro-electromechanical system switching devices; anda circuit breaker component, wherein the circuit breaker component is operably associated with the over-current protective component.

2. A MEMS micro-switch array based current bruiting enabled circuit interrupting apparatus, the apparatus comprising:an over-current protective component, the over-current protective component comprising:a switching circuit, wherein the switching circuit comprises a plurality of micro-electromechanical system switching devices; anda switching component, the switching component being operably associated with the over-current protection component, wherein the switching component is configured to be manually or automatically opened.

3. The apparatus of claim 1, wherein the over-current protective component further comprises a user interface, wherein the user interface is configured to receive input control commands.

4. The apparatus of claim 3, wherein the over-current protective component further comprises a logic circuit in communication with the user interface.

5. The apparatus of claim 4, wherein the over-current protective component further comprises a power stage circuit, the power stage circuit being in communication with the logic circuit.

6. The apparatus of claim 5, wherein the over-current protective component further comprises an MEMS protection circuit that is in communication with the logic circuit, the switching circuit, and the power staging circuit.

7. The apparatus of claim 6, wherein the logic circuit is configured to monitor a load current.

8. The apparatus of claim 7, wherein the logic circuit is configured to monitor a load voltage.

9. The apparatus of claim 8, where in response to a monitored load current or load voltage varying from a predetermined value, a fault signal is generated and transmitted to the MEMS protection circuit.

10. The apparatus of claim 9, where in response to the received fault signal, the over-current protective circuit diverts a load current from the micro-electromechanical system switching devices of the switching circuit.

11. The apparatus of claim 10, where the micro-electromechanical system switches are opened in response to the diversion of the load current.

12. The apparatus of claim 11, wherein the micro-electromechanical system switches of the switching circuit are configured to open prior to the tripping of the circuit breaker component.

13. A method for implementing a MEMS micro-switch array based current limiting enabled circuit interrupting apparatus, the method comprising:physically associating an over-current protective component with a circuit breaker component, wherein the over-current protective component comprises a plurality of micro-electromechanical system switching devices;configuring the micro-electromechanical system switches to open prior to the tripping of the circuit breaker component;monitoring a load current value of a load current passing through the plurality of micro-electromechanical switching system devices;determining if the monitored load current value varies from a predetermined load current value;diverting the load current from the plurality of micro-electromechanical switching system devices in the event that the monitored load current value varies from a predetermined load current value.

14. The method of claim 13, wherein the over-current protective component is configured to receive input control commands.

15. The method of claim 14, wherein the over-current protective component is configured to monitor a load voltage.

16. The method of claim 15, where in response to a monitored load voltage varying from a predetermined value, the over-current protective component diverts a load current from the micro-electromechanical system switching devices.

17. The method of claim 16, where the micro-electromechanical system switches are opened in response to the diversion of the load current.
Description:

BACKGROUND OF THE INVENTION

[0001]Embodiments of the invention relate generally to a switching device for switching off a current in a current path, and more particularly to micro-electromechanical system based switching devices.

[0002]To protect against fire and equipment damage, electrical equipment and wiring must be protected from conditions that result in current levels above their ratings. Over-current conditions are classified by the time required before damage occurs and are grouped into two categories: timed over-currents and instantaneous over-currents.

[0003]Timed over-current faults are the less severe variety and require the protective equipment to deactivate the circuit after a given time period, which depends on the level of the fault. Timed over-current faults are typically current levels jest above rated and up to 8-10 times rated. The system cabling and equipment can handle these faults for a period of time but the protective equipment should deactivate the circuit if the current levels don't recede. Typically timed faults result from either mechanically overloaded equipment or high impedance paths between opposite polarity lines--line to line, line to ground, or line to neutral.

[0004]Instantaneous over-currents, also termed short circuit faults, are severe faults and involve current levels of 8-10 time rated current and above. These faults result from low impedance paths between opposite polarity lines--line to line, line to ground, or line to neutral--and need to be removed from the system immediately. Short circuit faults involve extreme currents and can be extremely damaging to equipment and dangerous to personnel. The longer these faults persist on the system the more energy is released and the more damage occurs. It is of vital importance to minimize the response time and thus the let-through energy during a short circuit fault.

[0005]A circuit breaker is an electrical device designed to protect electrical equipment from damage caused by faults in the circuit. Traditionally, most conventional circuit breakers include bulky electromechanical switches. Unfortunately, these conventional circuit breakers are large in size thereby necessitating use of a large force to activate the switching mechanism. Additionally, the switches of these circuit breakers generally operate at relatively slow speeds. Further, these circuit breakers are disadvantageously complex to build, and thus expensive to fabricate. In addition, when contacts of a switching mechanism within a conventional circuit breaker are physically separated, an arc is typically formed between the contacts and continues to carry current until the current in the circuit ceases. Moreover, energy associated with the arc is generally undesirable to both equipment and personnel,

[0006]A contactor is an electrical device that is designed to switch an electrical load ON and OFF upon command. Traditionally, electromechanical contactors are employed in control gear, where the electromechanical contactors are capable of handling switching currents up to their interrupting capacity. Electromechanical contactors may also find application in power systems for switching currents. However, fault currents in power systems are typically greater than the interrupting capacity of the electromechanical contactors. Accordingly, to employ electromechanical contactors in power system applications it may be desirable to protect the contactor from damage by backing it up with a series device that is sufficiently fast acting to interrupt fault currents prior to the contactor opening at ail values of current above the interrupting capacity of the contactor.

[0007]Electrical systems presently use either a fuse or a circuit breaker to perform over-current protection. Fuses rely on heating effects (i.e., I2t) to operate. They are designed as weak points in the circuit and each successive fuse closer to the load must be rated for smaller and smaller currents. In a short circuit condition all upstream fuses see the same heating energy and the weakest one, by design the closest to the fault, will be the first to operate. Fuses, however, are one-time devices and must be replaced after a fault occurs.

[0008]Previously conceived solutions to facilitate use of contactors in power systems have include vacuum contactors, vacuum interrupters and air break contactors. Unfortunately, contactors such as vacuum contactors do not lend themselves to easy visual inspection as the contactor tips are encapsulated in a sealed, evacuated enclosure. Further, while the vacuum contactors are well suited for handling the switching of large motors, transformers and capacitors, they are known to cause damaging transient over voltages, particularly when the load is switched off.

[0009]Further, electromechanical contactors generally use mechanical switches. However, as these mechanical switches tend to switch at a relatively slow speed predictive techniques are required in order to estimate occurrence of a zero crossing, often tens of milliseconds before the switching event is to occur. Such zero crossing prediction is prone to error as many transients may occur in this time.

[0010]As an alternative to slow mechanical and electromechanical switches, fast solid-state switches have been employed in high speed switching applications. As will be appreciated, these solid-state switches switch between a conducting state and a non-conducting state through controlled application of a voltage or bias. For example, by reverse biasing a solid-state switch, the switch may be transitioned into a non-conducting state. However, since solid-state switches do not create a physical gap between contacts when they are switched into a non-conducing state, they experience leakage current. Further, due to internal resistances, when solid-state switches operate in a conducting state, they experience a voltage drop. Both the voltage drop and leakage current contribute to the generation of excess heat under normal operating circumstances, which may be detrimental to switch performance and life. Moreover, due at least in part to the inherent leakage current associated with solid-state switches, their use in circuit breaker applications is not possible.

BRIEF DESCRIPTION OF THE INVENTION

[0011]Exemplary embodiments of the present invention comprise a micro-electromechanical system (MEMS) micro-switch array based current limiting enabled circuit interrupting apparatus. The apparatus comprising an over-current protective component, wherein die over-current protective component comprises a switching circuit, wherein the switching circuit comprises a plurality of micro-electromechanical system switching devices. The apparatus also comprises a circuit interrupting component, wherein the circuit interrupting device is in operable communication with the over-current protective component.

[0012]Another exemplary embodiment of the present invention comprises a method for implementing a MEMS micro-switch array based current limiting enabled circuit interrupting apparatus. The method comprises physically associating an over-current protective component with a circuit breaker component, wherein the over-current protective component comprises a plurality of micro-electromechanical system switching devices and configuring the micro-electromechanical system switches to open prior to the tripping of the circuit breaker component. The method further comprises monitoring a load current value of a load current passing through the plurality of micro-electromechanical switching system devices and determining if the monitored load current value varies from a predetermined load current value. Yet further, the method comprises diverting the load current from the plurality of micro-electromechanical switching system devices in the event that the monitored load current value varies front a predetermined load current value.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:

[0014]FIG. 1 is a block diagram of an exemplary MEMS based switching system in accordance with an embodiment of the invention.

[0015]FIG. 2 is schematic diagram illustrating the exemplary MEMS based switching system depicted in FIG. 1.

[0016]FIG. 3 is a block diagram of an exemplary MEMS based switching system in accordance with an embodiment of the invention and alternative to the system depicted in FIG. 1.

[0017]FIG. 4 is a schematic diagram illustrating the exemplary MEMS based switching system depicted in FIG. 3.

[0018]FIG. 5 is a block diagram of an exemplary MEMS based over-current protective component in accordance with an embodiment of the present invention.

[0019]FIG. 6 is a block diagram of an exemplary MEMS enabled circuit interrupting apparatus comprising a circuit breaker in accordance with an embodiment of the present invention.

[0020]FIG. 7 is a block diagram of an exemplary MEMS enabled circuit interrupting apparatus comprising a switching component in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0021]In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments of the present invention. However, those skilled in the art will understand that embodiments of the present invention may be practiced without these specific details, that the present invention is not limited to the depicted embodiments, and that the present invention may be practiced in a variety of alternative embodiments. In other instances, well known methods, procedures, and components have not been described in detail.

[0022]Further, various operations may be described as multiple discrete steps performed in a manner that is helpful for understanding embodiments of the present invention. However, the order of description should not be construed as to imply that these operations need be performed in the order they are presented, or that they are even order dependent. Moreover, repeated usage of the phrase "in an embodiment" does not necessarily refer to the same embodiment, although it may. Lastly, the terms "comprising," "including," "having," and the like, as used in the present application, are intended to be synonymous unless otherwise indicated.

[0023]FIG. 1 illustrates a block diagram of an exemplary arc-less MEMS based switching system 10, in accordance with aspects of the present invention. Presently, MEMSs generally refers to micron-scale structures that, for example, can integrate a multiplicity of functionally distinct elements. Such elements including, but not being limited to, mechanical elements, electromechanical elements, sensors, actuators, and electronics, on a common substrate through micro-fabrication technology. It Is contemplated, however, that many techniques and structures presently available in MEMS devices will in just a few years be available via nanotechnology-based devices, that is, structures that may be smaller than 100 nanometers in size. Accordingly, even though example embodiments described throughout this document may refer to MEMS-based switching devices, it is submitted that the inventive aspects of the present invention should be broadly construed and should not be limited to micron-steed devices.

[0024]As illustrated in FIG. 1, the arc-less MEMS based switching system 10 is shown as including MEMS based switching circuitry 12 and arc suppression circuitry 14, where the arc suppression circuitry 14 (alternatively referred to Hybrid Arc-less Limiting Technology (HALT), is operatively coupled to the MEMS based switching circuitry 12. Within exemplary embodiments of the present invention, the MEMS based switching circuitry 12 may be integrated in its entirety with the arc suppression circuitry 14 in a single package 16. In further exemplar embodiments, only specific portions or components of the MEMS based switching circuitry 12 may be integrated in conjunction with the arc suppression circuitry 14.

[0025]In a presently contemplated configuration as will be described in greater detail with reference to FIG. 2, the MEMS based switching circuitry 12 may include one or more MEMS switches. Additionally, the arc suppression circuitry 14 may include a balanced diode bridge and a pulse circuit. Further, the arc suppression circuitry 14 may be configured to facilitate suppression of an are formation between contacts of the one or more MEMS switches. It may be noted that the arc suppression circuitry 14 may be configured to facilitate suppression of an arc formation in response to an alternating current (AC) or a direct current (DC).

[0026]Turning now to FIG. 2, a schematic diagram 18 of the exemplary arc-less MEMS based switching system depicted in FIG. 1 is illustrated in accordance with an embodiment. As noted with reference to FIG. 1, the MEMS based switching circuitry 12 may include one or more MEMS switches. In the illustrated exemplary embodiment, a first MEMS switch 20 is depicted as having a first contact 22, a second contact 24 and a third contact 26. In one embodiment, the first contact 22 may be configured as a drain, the second contact 24 may be configured as a source and the third contact 26 may be configured as a gate. Further, as illustrated in FIG. 2, a voltage snubber circuit 33 may be coupled in parallel with the MEMS switch 20 and configured to limit voltage overshoot during fast contact separation as will be explained in greater detail hereinafter. In further embodiments, the snubber circuit 33 may include a snubber capacitor (see 76, FIG. 4) coupled in series with a snubber resistor (see FIG. 4, reference number 78). The snubber capacitor may facilitate improvement in transient voltage sharing during the sequencing of the opening of the MEMS switch 20. Additionally, the snubber resistor may suppress any pulse of current generated by the snubber capacitor during closing operation of the MEMS switch 20. In yet further embodiments, the voltage snubber circuit 33 may include a metal oxide varistor (MOV) (not shown).

[0027]In accordance with further aspects of the present technique, a load circuit 40 may be coupled in series with the first MEMS switch 20. The load circuit 40 may include a voltage source VBUS 44. In addition, the load circuit 40 may also include a load inductance 46 LLOAD, where the load inductance LLOAD 46 is representative of a combined load inductance and a bus inductance viewed by the load circuit 40. The load circuit 40 may also include a load resistance RLOAD 48 representative of a combined load resistance viewed by the load circuit 40. Reference numeral 50 is representative of a load circuit current ILOAD that may flow through the load circuit 40 and the first MEMS switch 20.

[0028]As noted with reference to FIG. 1, the arc suppression circuitry 14 may include a balanced diode bridge. In the illustrated embodiment, a balanced diode bridge 28 is depicted as having a first branch 29 and a second branch 31. As used herein, the term "balanced diode bridge" is used to represent a diode bridge that is configured in such a manner that voltage drops across both the first and second branches 29, 31 are substantially equal. The first branch 29 of the balanced diode bridge 28 may include a first diode D1 30 and a second diode D2 32 coupled together to form a first series circuit. In a similar fashion, the second branch 31 of the balanced diode bridge 28 may include a third diode D3 34 and a fourth diode D4 36 operatively coupled together to form a second series circuit.

[0029]In an exemplary embodiment, the first MEMS switch 20 may be coupled in parallel across midpoints of the balanced diode bridge 28. The midpoints of the balanced diode bridge may include a first midpoint located between the first and second diodes 30, 32 and a second midpoint located between the third and fourth diodes 34, 36. Further, the first MEMS switch 20 and the balanced diode bridge 28 may be tightly packaged to facilitate minimization of parasitic inductance caused by the balanced diode bridge 28 and in particular, the connections to the MEMS switch 20. It must be noted that, in accordance with exemplary aspects of the present technique, the first MEMS switch 20 and the balanced diode bridge 28 are positioned relative to one another such that the inherent inductance between the first MEMS switch 20 and the balanced diode bridge 28 produces a di/dt voltage less than a few percent of the voltage across the drain 22 and source 24 of the MEMS switch 20 when carrying a transfer of the load current to the diode bridge 28 during the MEMS switch 20 turn-off which will be described in greater detail hereinafter. In further embodiments, the first MEMS switch 20 may be integrated with the balanced diode bridge 28 in a single package 38 or optionally within the same die with the intention of minimizing the inductance interconnecting the MEMS switch 20 and the diode bridge 28.

[0030]Additionally, the arc suppression circuitry 14 may include a pulse circuit 52 operatively coupled in association with the balanced diode bridge 28. The pulse circuit 52 may be configured to detect a switch condition and initiate opening of the MEMS switch 20 responsive to the switch condition. As used herein, the term "switch condition" refers to a condition that triggers changing a present operating state of the MEMS switch 20. For example, the switch condition may result in changing a first closed state of the MEMS switch 20 to a second open state or a first open state of the MEMS switch 20 to a second closed state. A switch condition may occur in response to a number of actions including but not limited to a circuit fault or switch ON/OFF request.

[0031]The pulse circuit 52 may include a pulse switch 54 and a pulse capacitor CPULSE 56 series coupled to the pulse switch 54. Further, the pulse circuit may also include a pulse inductance LPULSE 58 and a first diode DP 60 coupled in series with the pulse switch 54. The pulse inductance LPULSE 58, the diode DP 60, the pulse switch 54 and the pulse capacitor CPULSE 56 may be coupled in series to form a first branch of the pulse circuit 52, where the components of the first branch may be configured to facilitate pulse current shaping and timing. Also, reference numeral 62 is representative of a pulse circuit current IPULSE that may flow through the pulse circuit 52.

[0032]In accordance with aspects of the present invention, the MEMS switch 20 may be rapidly switched (for example, on the order of picoseconds or nanoseconds) from a first closed state to a second open state while carrying a current albeit at a near-zero voltage. This may be achieved through the combined operation of the load circuit 40, and pulse circuit 52 including the balanced diode bridge 28 coupled in parallel across contacts of the MEMS switch 20.

[0033]Reference is now made to FIG. 3, which illustrates a block diagram of an exemplary soft switching system 11, in accordance with aspects of the present invention. As illustrated in FIG. 3, the soft switching system 11 includes switching circuitry 12, detection circuitry 70, and control circuitry 72 operatively coupled together. The detection circuitry 70 may be coupled to the switching circuitry 12 and configured to detect an occurrence of a zero crossing of an alternating source voltage in a load circuit (hereinafter "source voltage") or an alternating current in the load circuit (hereinafter referred to as "load circuit current"). The control circuitry 72 may be coupled to the switching circuitry 12 and the detection circuitry 70, and may be configured to facilitate arc-less switching of one or more switches in the switching circuitry 12 responsive to a detected zero crossing of the alternating source voltage or the alternating load circuit current. In one embodiment, the control circuitry 72 may be configured to facilitate arc-less switching of one or more MEMS switches comprising at least part of the switching circuitry 12.

[0034]In accordance with one aspect of the invention, the soft switching system 11 may be configured to perform soft or point-on-wave (PoW) switching whereby one or more MEMS switches in the switching circuitry 12 may be closed at a time when the voltage across the switching circuitry 12 is at or very close to zero and opened at a time when the current through the switching circuitry 12 is at or close to zero. By closing the switches at a time when the voltage across the switching circuitry 12 is at or very close to zero, pre-strike arcing can be avoided by keeping the electric field low between the contacts of the one or more MEMS switches as they close; even if multiple switches do not all close at the same time. Similarly, by opening the switches at a time when the current through the switching circuitry 12 is at or close to zero, the soft switching system 11 can be designed so that the current in the last switch to open in the switching circuitry 12 falls within the design capability of the switch. As mentioned above, the control circuitry 72 may be configured to synchronize the opening and closing of the one or more MEMS switches of the switching circuitry 12 with the occurrence of a zero crossing of an alternating source voltage or an alternating load circuit current.

[0035]Turning to FIG. 4, a schematic diagram 19 of one embodiment of the soft switching system 11 of FIG. 3 is illustrated. In accordance with the illustrated embodiment, the schematic diagram 19 includes one example of the switching circuitry 12, the detection circuitry 70 and the control circuitry 72.

[0036]Although for the purposes of description, FIG. 4 illustrates only a single MEMS switch 20 in switching circuitry 12, the switching circuitry 12 may nonetheless include multiple MEMS switches depending upon, for example, the current and voltage handling requirements of the soft switching system 11. In an exemplary embodiment, the switching circuitry 12 may include a switch module including multiple MEMS switches coupled together in a parallel configuration to divide the current amongst the MEMS switches. In a further exemplary embodiment, the switching circuitry 12 may include an array of MEMS switches coupled in a series configuration to divide the voltage amongst the MEMS switches. In a yet further exemplary embodiment, the switching circuitry 12 may include an array of MEMS switch modules coupled together in a series configuration to concurrently divide the voltage amongst the MEMS switch modules and divide the current amongst the MEMS switches in each module. Furthermore, the one or more MEMS switches of the switching circuitry 12 may be integrated into a single package 74.

[0037]The exemplary MEMS switch 20 may include three contacts. In an exemplary embodiment, a first contact may be configured as a drain 22, a second contact may be configured as a source 24, and the third contact may be configured as a gate 26. In one embodiment, the control circuitry 72 may be coupled to the gate contact 26 to facilitate switching a current state of the MEMS switch 20. Also, in additional exemplary embodiments damping circuitry (snubber circuit) 33 may be coupled in parallel with the MEMS switch 20 to delay appearance of voltage across the MEMS switch 20. As illustrated, the damping circuitry 33 may include a snubber capacitor 76 coupled in series with a snubber resistor 78.

[0038]The MEMS switch 20 may be coupled in series with a load circuit 40, as further illustrated in FIG. 4. In a presently contemplated configuration, the load circuit 40 may include a voltage source VSOURCE 44, and may possess a representative load inductance LLOAD 46 and a load resistance RLOAD 48. In one embodiment, the voltage source VSOURCE 44 (also referred to as an AC voltage source) may be configured to generate the alternating source voltage and the alternating load current ILOAD 50.

[0039]As previously noted, the detection circuitry 70 may be configured to detect occurrence of a zero crossing of the alternating, source voltage or the alternating load current ILOAD 50 in the load circuit 40. The alternating source voltage may be sensed via the voltage sensing circuitry 80 and the alternating load current ILOAD 50 may be sensed via the current sensing circuitry 82. The alternating source voltage and the alternating load current may be sensed continuously or at discrete periods for example.

[0040]A zero crossing of the source voltage may be detected through, for example, use of a comparator such as the illustrated zero voltage comparator 84. The voltage sensed by the voltage sensing circuitry 80 and a zero voltage reference 86 may be employed as inputs to the zero voltage comparator 84. In turn, an output signal 88 representative of a zero crossing of the source voltage of the load circuit 40 may be generated. Similarly, a zero crossing of the toad current ILOAD 50 may also be detected through use of a comparator such as the illustrated zero current comparator 92. The current sensed by the current sensing circuitry 82 and a zero current reference 90 may be employed as inputs to the zero current comparator 92. In turn, an output signal 94 representative of a zero crossing of the load current ILOAD 50 may be generated.

[0041]The control circuitry 72, may in turn utilize the output signals 88 and 94 to determine when to change (for example, open or close) the current operating state of the MEMS switch 20 (or array of MEMS switches). More specifically, the control circuitry 72 may be configured to facilitate opening of the MEMS switch 20 in an arc-less manner to interrupt or open the load circuit 40 responsive to a detected zero crossing of the alternating load current ILOAD 50. Additionally, the control circuitry 72 may be configured to facilitate closing of the MEMS switch 20 in an arc-less manner to complete the load circuit 40 responsive to a detected zero crossing of the alternating source voltage.

[0042]The control circuitry 72 may determine whether to switch the present operating state of the MEMS switch 20 to a second operating state based at least in part upon a state of an Enable signal 96. The Enable signal 96 may be generated as a result of a power off command in a contactor application, for example. Further, the Enable signal 96 and the output signals 88 and 94 may be used as input signals to a dual D flip-flop 98 as shown. These signals may be used to close the MEMS switch 20 at a first source voltage zero after the Enable signal 96 is made active (for example, rising edge triggered), and to open the MEMS switch 20 at the first load current zero after the Enable signal 96 is deactivated (for example, failing edge triggered). With respect to the Illustrated schematic diagram 19 of FIG. 4, every time the Enable signal 96 is active (either high or low depending upon the specific implementation) and either output signal 88 or 94 indicates a sensed voltage or current zero, a trigger signal 172 may be generated. Additionally, the trigger signal 172 may be generated via a NOR gate 100. The trigger signal 102 may in turn be passed through a MEMS gate driver 104 to generate a gate activation signal 106 which may be used to apply a control voltage to the gate 26 of the MEMS switch 20 (or gates in the case of a MEMS array).

[0043]As previously noted, in order to achieve a desirable current rating for a particular application, a plurality of MEMS switches may be operatively coupled in parallel (for example, to form a switch module) in lieu of a single MEMS switch. The combined capabilities of the MEMS switches may be designed to adequately carry the continuous and transient overload current levels that may be experienced by the load circuit. For example, with a 10-amp RMS motor contactor with a 6× transient overload, there should be enough switches coupled in parallel to carry 60 amps RMS for 10 seconds. Using point-on-wave switching to switch the MEMS switches within 5 microseconds of reaching current zero, there will he 160 milliamps instantaneous, flowing at contact opening. Thus, for that application, each MEMS switch should be capable of "warm-switching" 160 milliamps, and enough of them should be placed in parallel to carry 60 amps. On the other hand, a single MEMS switch should be capable of interrupting the amount of current that will be flowing at the moment of switching.

[0044]FIG. 5 shows a block diagram of a MEMS based over-current protection device 110 that may be implemented within exemplary embodiments of the present invention. The device 110 receives user control inputs at the user interface 115, the user interface 115 providing a control and input interface for a user to interact with the device 110. Within the user interface 115, three-phase line power inputs 114 are received at a terminal block 116, wherein the line power input 114 is fed to the terminal block 116, and then respectively through to the power circuit 135 and the switch module 120.

[0045]User input can be in the form of input from a trip adjustment potentiometer, an electrical signal from a human interface (for example, from a push-button interface), or control equipment that are routed to the user interface 115. User input is used to control the MEMS switching as well as provide user adjustability in regard to trip-time curves. The power circuit 135 performs basic functions to provide power for the additional circuits, such as transient suppression, voltage scaling & isolation, and EMI filtering.

[0046]The over-current protection device 110 further comprises logic circuitry 125; wherein the logic circuitry 125 is responsible controlling the normal operation as well as recognizing fault conditions (such as setting the trip-time curve for timed over-currents (126), allowing programmability or adjustability, controlling the closing/re-closing of specified logic (126, 128), etc . . . ). The current/voltage sensing component 127 provides the voltage and current measurements needed to implement the required logic for over-current protection operations, and for maintaining responsibility the energy diversion circuits utilize for cold switching operations, wherein the operations are accomplished using the above mentioned charging 132 and pulse circuits 133 in addition to the diode bridge 134. The MEMS protection circuitry 130 is similar in configuration and operation to the pulse circuit 52 as described above.

[0047]Lastly, the switching circuitry 120 is implemented, wherein the switching circuit comprises a switching module 122 containing the MEMS device arrays. The switching module 122 is similar in configuration and operation to the MEMS switch 20 as described above. The switching circuit 120 further being responsible for the output delivery of a three-phase load current 141 to any downstream equipment.

[0048]Within exemplary embodiments of the present invention, power for the logic circuit 125 is drawn from a phase-to-phase differential and fed through a surge suppression component 136. A main power stage component 137 distributes power at various voltages in order to feed the control logic 138, the over-current protection device charging circuits 139, and the MEMS switch gate voltages 140. A current and voltage sensor 127 feeds the timed and instantaneous over-current logic 128, which in turn controls the MEMS switch gate voltage 140 and the MEMS protection circuit's 130 triggering circuits 131.

[0049]The current/voltage sensor 127 of the over-current protection component 110 continuously monitors either a current level or a voltage level within a system. As implemented, the current/voltage detector is responsible for determining if the level of the current/voltage has varied from a predetermined value. In the event that the monitored current/voltage levels do vary from a predetermined value, a fault signal is generated at the instantaneous over-current logic 128 to indicate that a system determined variance in current/voltage level has been detected. Thereafter, the fault signal is delivered to the trigger circuit 131, wherein the trigger circuit initiates an MEMS protection pulsing operation at the MEMS protection circuit 130. The pulsing operation involves the activation of the pulse circuit 133, the activation of which results in the closing of the LC pulse circuit. Once the LC pulse circuit 133 has been closed the charging circuit 132 discharges through the balanced diode bridge 134. The pulse current through the diode bridge 134 creates a resulting short across the MEMS array switches of the switching module 122 and diverts the load current into the diode bridge and around the MEMS array (see FIGS. 2 and 5). Under the protective pulse operation, the MEMS switches of the switch module 122 can be opened with a zero or close to zero current.

[0050]Within additional exemplary embodiments of the present invention the over-current protection functionality of the MEMS protection arc suppression circuitry is used in conjunction with MEMS switches and supplementary logic circuitry in such a manner as to place it in series with an existing circuit interrupting device (for example, a circuit breaker or a switch). As illustrated in FIGS. 6 and 7 respectively, within exemplary embodiments of the present invention, the MEMS over-current protection device 110 can be configured in series with either a circuit breaker 155, such as an industrial circuit breaker having an operating mechanism with an operating handle, a set of current sensors, an electronic trip unit, a set of separable contact arms in operable communication with the operating mechanism, and an interruption chamber for example, or a switching device 165, such as an in-line set of contacts with an operating handle to open and close the contacts for example. Typical circuit breakers 155 and switches 165 are well known in the art, and require no further description here. As such, the current limiting capabilities of the MEMS switches have the capability to protect the circuit interrupter during fault conditions; that is tripping before the current interrupter has time to open and generate a resulting arc. In further exemplary embodiments of the present invention the switching device can comprise a plurality of switching devices (for example, simple semiconductor switches, simple electrical switches, etc., or other switching devices suitable for the purposes disclosed herein).

[0051]Such series-connected configurations further provide an apparatus or device with the capability to boost the interruption rating of a circuit breaker. The apparatus or device could be configured as a supplemental add-on for existing circuit interrupters or integrated within a stand-alone housing along with the circuit interrupter. In particular, this dual concept configuration eliminates the need for the implementation of isolation contactors and disconnect switches within an over-current protection device. Further, this configuration would allow users to upgrade a power systems protection capability with little maintenance and cost.

[0052]While only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
Jorge Polentino

A LONG LIFETIME, LOW VOLTAGE, CAPACITIVE RF MICROSWITCH

Micromechanical switches have the capability to offer substantial advantages over their conventional semiconductor counterparts, such as low power consumption, very high isolation, low insertion loss, linear performance and low cost. Expected applications include such areas as high-isolation switching networks, phase shifters and reconfigurable filters, for use in phased-array antennas or filter-path selection in multi-band communications systems at high frequencies (10-100GHz) [1-3]. This paper demonstrates a low-voltage, capacitive shunt microswitch that has a lifetime of greater than five billion switching cycles.

The physical implementation of the capacitive shunt switch consists of a grounded metallic membrane supported a few microns over a passivated coplanar waveguide (CPW) transmission line, Figure 1. During operation of the switch, an RF (radio-frequency) signal and DC bias voltage are superimposed and applied to the signal line input port. In the switch 'on' state, the DC bias is zero, the membrane remains up and the capacitance of the switch is low (of the order of 1-100fF), allowing the RF signal to pass to the output port unimpeded. Increasing the DC bias voltage causes the membrane to pull down to the intermetal


dielectric due to the electrostatic force between the membrane and transmission line. This increases the capacitance to 1-10pF, shorting the RF signal to ground, and turning the switch 'off'. Removal of the DC bias allows the bridge to return to its original position because of the mechanical restoring forces exerted by the membrane anchors. A simplified circuit diagram for the shunt switch is shown in Figure 2.




RELIABILITY ISSUES
For conventional switch designs, the bias voltage required to turn off the switch is often relatively high (30-100V). This high voltage necessitates the use of up-converter circuitry and can be difficult to achieve in certain portable wireless communications applications. More importantly, the high electric fields set up across the thin dielectric while the switch is in the 'off' state can cause electrons to be injected into or removed from the dielectric layer. This is known as dielectric charging, and the resultant parasitic charge buildup leads to a shift in the pull-down voltage of the switch equal to




if the charge is assumed to be located at the dielectric-air interface and have surface density Qp, and Cd is the dielectric capacitance per unit area [4-7]. This shift in the pull-in voltage is necessary to compensate for the reduced electric field in the airgap due to the charge at the dielectric surface. It is clear that if the voltage shift exceeds the applied voltage, the switch will fail to actuate and remain 'on'. Alternatively, the switch can fail in the 'off' state due to the attractive force between the charge and metal membrane.

Dielectric charging is strongly dependant on bias voltage, and it has been suggested by Goldsmith et al that a tenfold increase in lifetime results from reducing the required bias voltage by 6-7V [7].

Since mechanical failures are now relatively rare in MEMS, charging has become the dominant failure mechanism of these devices. Almost all capacitive microswitches suffer to some degree from a dielectric charging problem, and it is important that the effect be minimised if such switches are to become commercially successful.
This work concentrates on reducing the dielectric charging problem by reducing the voltage needed to actuate the switch and by using a high-quality silicon oxide as the dielectric layer.

DESIGN
Meander-type tethers are used to suspend the central switch membrane, Figure 1, resulting in a low pull-down voltage (~15V) whilst maintaining reliability. A stress gradient of approximately 200MPa/μm exists in the aluminium film, but this is negated by the placement of the supporting tethers on the diagonal at the membrane corners. The result is a membrane that exhibits a maximum convex bow of 0.5-1.0μm over its width of 200μm. This symmetrical bowing reduces up-state capacitance and hence insertion loss, and so is advantageous rather than being a problem. Perforations in the membrane allow for easy removal of sacrificial layer and enable faster switching speeds by reducing damping.
By using silicon oxide as a dielectric layer, the problems due to dielectric charging are further reduced, although a drawback associated with this is the slight loss of isolation in the off state, due to the relatively low dielectric constant of silicon oxide [2].

FABRICATION FLOW
A device schematic is illustrated in Figure 3. The switch is surface micromachined using the low-temperature (<350oc)


ELECTROMECHANICAL RESULTS
Including corrections for electrostatic fringing fields and the voltage offset due to dielectric charging of the intermetal dielectric, the pull-down voltage for the devices may be approximated by


where k is the effective spring constant of the structure, fc is a correction for electrostatic fringing fields, A is the membrane area, εo is the permittivity of free space, and go the initial airgap spacing. VQ is the voltage shift due to trapped charge in the dielectric layer.

Using finite element simulations [9], the spring constant for the 200 x 200μm2 device shown in Figure 1 has been evaluated as 2.35Nm-1, and the fringing field correction factor can be as high as 1.2 for an airgap of 5μm. The density of the trapped charge at the oxide surface has been evaluated to be -5.5 x 1010e/cm2. More information on this model is in [10].Pull-down voltages for a number of devices of varying airgap height are illustrated in Figure 4; measured and modelled results are in good agreement. For comparison, results for switches measuring 100 x 100μm2 are also illustrated, although the high pull-down voltages and low isolation exhibited by these devices means they may be of limited interest.

RADIO-FREQUENCY RESULTS
The RF performance of a typical switch is shown in Figure 5. The device membrane measures 200 x 200μm2 and has an airgap of approximately 5μm. Dielectric thickness is 100nm. Six closely spaced switches have been measured and the results averages. Switching voltage is (14.8 +/- 0.8)V, and switching speed is estimated to be approximately 15μs [2]. RF analysis takes place on a Cascade Microtech probe station using a HP8722D network analyser, and measurements have been de-embedded by subtracting the attenuation of a through line of identical dimensions to the device line from all measurements. At 30GHz, average insertion loss and isolation are -0.2dB and -19.0dB, respectively.


LIFETIME PERFORMANCE
For the designs used here, PECVD silicon oxide is the intermetal dielectric, instead of the more commonly used silicon nitride. The oxide has a lower dielectric constant than the more commonly used silicon nitride, (εr = 5.0 instead of 7.0), and because isolation depends on the dielectric permittivity, some reduction in isolation is expected. However, silicon oxide is a much better quality dielectric and does not suffer from the same level of dielectric charging [2, 10].

This was followed by a 'hold-down test', in which the switch was held in the down state at a bias voltage of 16V for a period of 18 hours, without any adverse effects. The switch returned to the up-state immediately the bias was removed, with a change of less than 1.5% in the down-state capacitance over the length of the test. More recently, a 200 x 200μm2 switch (pull-down voltage 12V) was actuated over 5.5 billion times without failure at a bias voltage of 16V and frequency of 5kHz. These tests have been stopped due to time constraints on equipment, and it is expected that substantial increases in this lifetime can be made as time permits.

A long-lifetime, low-voltage micromechanical shunt switch has been demonstrated. The capacitive structure is completely CMOS compatible and has a pull-in voltage of approximately 15V. Radio-frequency performance is promising; insertion loss is -0.2dB and isolation is -19.0dB at 30GHz.
Jorge Polentino
CRF
http://www.tyndall.ie/open-admin/publications/MME-2004.pdf

DISEÑO DE UN SISTEMA DE COMUNICACIÓN RF DE MUY BAJO CONSUMO

Actualmente la conectividad a través de redes inalámbricas presenta una amplia variedad de soluciones, pero la mayoría de ellas están enfocadas a intercambiar grandes volúmenes de información, haciéndolas inapropiadas para un número de aplicaciones caracterizadas por una cantidad pequeña de información, grandes tiempos de latencia y la necesidad de bajos consumos de potencia y bajo costo. En este contexto la IEEE desarrolló el estándar IEEE 802.15.4 [1], se creó la alianza Zigbee [2] entre un grupo de empresas y existen varios esfuerzos en investigación actualmente [3,4].

El propósito de este trabajo fue diseñar un sistema basado en componentes estándar que contemple los requerimientos mencionados anteriormente. Esto permitió explorar técnicas a nivel de sistema y compromisos para alcanzar bajo consumo de potencia y tamaño, previo al diseño de circuitos integrados.

Los ejemplos de posibles aplicaciones son enormes: industriales ( e.g. sistemas de sensado o alarmas en lugares difíciles de alcanzar), agrícolas (e.g. redes de sensores para monitorear el estado del suelo o las condiciones climáticas), domésticas (control centralizado de dispositivos electrónicos de una casa), médicos, etc.

Requerimientos iniciales para el sistema

El sistema esta compuesto por dos dispositivos. Una base fija y un dispositivo remoto. Este último, alimentado por batería, envía a la base información que puede provenir de alguna clase de sensor. El enlace es bidireccional.

La frecuencia portadora fue seleccionada en el rango de 400MHz (cercana la banda ISM de 433 MHz). El objetivo es obtener un consumo tal que, con el dispositivo remoto transmitiendo constantemente 10 bytes/seg., la duración de una batería comercial de 2.8v y 1000mA/h debe ser mayor a un año. El mínimo rango de comunicación se especificó para 10m y el sistema debe tolerar un movimiento relativo de al menos 0.4m/seg. entre la base y el sistema remoto. Como meta adicional, el tamaño y el costo por unidad del dispositivo remoto debe minimizarse tanto como sea posible.

DESCRIPCIÓN GENERAL DEL SISTEMA
Cuatro bloques componen el sistema completo. Estos son: el transmisor de RF, un microcontrolador, las antenas y las redes de adaptación. Cada uno de estos bloques fue estudiado y optimizado separadamente en orden de obtener la mejor performance globalmente.
Para el transmisor de RF, se utilizó el chip XE1201A de la empresa Xemics, luego de un exhaustivo estudio de mercado. Sus mayores ventajas son el bajo consumo con potencia de salida programable, bajo voltaje de operación y pocos componentes externos. El microcontrolador usado para controlar el transceptor e implementar la interfaz con el sensor externo es el PIC16F628 de Microchip. Los requerimientos principales para el microcontrolador fueron un bajo voltaje de alimentación y un bajo consumo, permitiendo la posibilidad de utilizar un modo "sleep" (apagado) entre transmisiones de datos consecutivas.

TRANSCEPTOR RF
El XE1201A fue diseñado para operar entre 300 y 500MHz, y optimizado para trabajar en la banda ISM de 433 MHz. La frecuencia portadora se selecciona por medio de un resonador externo del tipo SAW (Surface Acoustic Wave), el cual ayuda a reducir el consumo de potencia gracias a un tiempo de encendido corto. La comunicación es half duplex y usa la modulación FSK. Otras características del integrado son las siguientes:

- Rango de alimentación: entre 2.4 y 5.5V.
- Cuatro niveles programables de potencia de salida: -15dBm, -5dBm, 2.5dBm, 5dBm
- Consumo de potencia en modo transmisión para cada uno de los niveles de potencia antes indicados: 5.5mA, 8mA, 11mA y 13.5mA.
- Consumo de potencia en modo receptor: 6mA,
- Consumo de potencia en modo apagado:0.2uA
- Tasa de datos : entre 4kbps y 64kbps
- Sensibilidad (ber=1%): -102dBm @64kbps, -109dBm @8kbps

Para el sistema implementado, se seleccionó una frecuencia portadora de 418MHz y una tasa de datos de 60kbps.

El diagrama de bloques del transceptor es presentado en la figura 1. El camino de transmisión está mostrado en la parte más baja del diagrama. Un DDS (Direct Digital Synthesizer) genera señales digitales de seno y coseno que corresponden a las señales I y Q de la modulación FSK. La salida del modulador FSK es conectada a un amplificador de potencia.

El camino de recepción es mostrado en la parte superior de la figura 1. Este se compone de un amplificador de bajo ruido, un demodulador –que convierte la señal recibida a banda base- un filtro pasabajos, un limitador –para digitalizar la señal- y un demodulador FSK –para obtener el flujo de datos. Como una característica adicional, el circuito incluye un sincronizador de bit, basado en un PLL digital, para recuperar el reloj a partir de los datos transmitidos. Esto simplifica la recepción de los datos en el microcontrolador; aunque hace necesario agregar al comienzo de cada bloque de datos un número de bits

ANTENAS
Requerimientos de las antenas
Los requerimientos del sistema llevan a restricciones fuertes con respecto al tamaño y a la performance de las antenas. Una alta ganancia debe obtenerse para ahorrar potencia. La antena debe también ser pequeña para reducir las dimensiones del circuito final. Requerimientos adicionales: buena resistencia física, compacta, inmunidad a la presencia de objetos cercanos y al contacto con las manos.

La antena seleccionada es una antena de bucle pequeño ("small loop antenna") imlementada sobre el circuito impreso; la cual cumple los requerimientos anteriores. Este tipo de antena presenta un tamaño reducido en el rango de frecuencias utilizado y son robustas y compactas. A pesar que la ganancia de las antenas de bucle pequeño es pequeña comparado con otros tipos de antenas en la banda de frecuencia utillizada (monopolos de un cuarto de longitud de onda, antenas helicoidales, etc.), ésta es suficiente para la distancia de comunicación especificada para la aplicación. La pérdida de ganancia es entonces compensada con la reducción en tamaño.

Una ventaja adicional con el uso de las antenas de bucle pequeño es que su tamaño extremadamente reducido hace posible el uso de antenas separadas para transmitir y recibir. Esto simplifica las redes de adaptación de impedancias y hace innecesario la introducción de una llave de RF para conectar la antena al circuito de transmisión o al de recepción del transceptor.
Diseño de una antena de loop pequeño

El diseño de la antena esta basado en el modelo propuesto en [6]. Al ser una antena inductiva, el bucle pequeño necesita un capacitor para ser ajustada. Por tanto se utilizó un capacitor variable para asegurar un ajuste exacto un maximizar la ganancia de la antena. El ajuste es hecho en el propio circuito, realizando una comunicación con una antena de referencia –antena biconica- y ajustando el capacitor hasta que la máxima ganancia sea obtenida.

La parte real de la impedancia del bucle pequeño es menor a 1Ω, por lo que no es fácil adaptar esta resistencia con la impedancia de entrada y salida del transceptor de RF (alrededor de 1kΩ y 600Ω respectivamente). Para facilitar el diseño de la red de adaptación de impedancia, un transformador es incluido, como se aprecia en la figura 2. El segundo bucle agregado actúa como loop secundario del transformador, cambiando la impedancia aparente de la antena (aumentando efectivamente el valor de la parte real de la impedancia).
A los efectos de simplificar el diseño, las antenas de recepción y transmisión son idénticas. Sus respectivas redes de adaptación adaptan estas antenas al correspondiente circuito.
Características de las antenas
La siguiente tabla muestra las principales características de la antena diseñada.

REDES DE ADAPTACIÓN DE IMPEDANCIAS

Debido a que la mayor preocupación del diseño es minimizar el consumo de potencia del sistema, es vital evitar perdidas en los circuitos de radiofrecuencia. En orden de minimizar las perdidas de potencia causadas por el desapareo entre el transceptor de RF y las antenas, las redes de adaptación de impedancias fueron cuidadosamente diseñadas y ajustadas experimentalmente.
Como fue explicado anteriormente, dos redes son requeridas: la red de recepción -quien adapta la antena receptora a la entrada del transceptor-, y la red de transmisión, que adapta la antena de transmisión a la salida de RF del XE1201A. Cada una de estas redes fue implementada como la cascada de dos redes que, en su punto de unión, se ve una impedancia de 50Ω. Este método fue elegido por dos razones. Primeramente éste permite estudiar los componentes del sistema, colocando un analizador de espectro, con impedancia de 50Ω. Segundo, un estudio experimental y teórico muestra que las redes de dos etapas son más estables e insensibles a variaciones de componentes que una solución basada en una red de una sola etapa.
Metodología de diseño.

El diseño de las redes se realizó en dos etapas. Primero se efectuó un diseño teórico basado en las redes sugeridas por el fabricante del transceptor, el cual se adaptó para esta aplicación en particular. Para ello se utilizó el programa MIMP (Motorota Impedance Matching Network). Luego, los valores de los componentes finales son ajustados experimentalmente para adaptar las impedancias de la antena y del transceptor. Esto se realizó para considerar los efectos parásitos. Los ajustes experimentales llevan a la conclusión que las perdidas de potencia en la red de adaptación del circuito de recepción son muy sensibles al valor de un capacitor particular, entonces, un componente variable fue introducido.

El procedimiento de ajuste se realizó de la siguiente forma: para una red de transmisión, una antena de referencia es colocada a una distancia fija del circuito, y la potencia recibida por la antena (medida con un analizador de espectro) es maximizada. Para la red de recepción la misma antena es ahora utilizada para transmitir una señal fija, y señales de banda base análogas provista por el transmisor son usadas para medir la potencia recibida (estas señales corresponden a las señales I y Q demoduladas de la demodulación FSK).

Redes finales
Las redes diseñadas se muestran en la figura 3.








La red de transmisión incluye el circuito necesario para polarizar la etapa de salida en RF del transceptor. La razón para esta aparentemente compleja arquitectura de la red de recepción es el hecho que ésta debe adaptar la salida diferencial del XE1201A a una antena singe-ended.

PLACA DE CIRCUITO IMPRESO
Trabajando en bandas de frecuencia mayores a cientos de MHz implica que algunos efectos, insignificantes a bajas frecuencias, comienzan a ser críticos y deben ser considerados. Estos incluyen el tipo de componentes usados, su colocación y separación, la distribución de la alimentación y de las señales, y el ancho y separación de las pistas. Los siguientes párrafos destacan, de las consideraciones discutidas en la literatura [7,8], aquellas que fueron aplicadas mayormente en este diseño.

Selección de componentes

A altas frecuencias los componentes parásitos de resistencias, capacitores e inductores son relevantes, cambiando completamente la performance del circuito. Fueron elegidos capacitares cerámicos y inductores de montaje superficial, los que presentan frecuencias propias de resonancia en el rango de los GHz. Además, su tamaño reducido permite minimizar la distancia entre componentes, lo que es también crítico.

Distribución de alimentación y ruteo de pistas

El plano de tierra facilita el retorno de las señales de RF y de alimentación. Permitiendo a estas señales ir por el camino de mínima impedancia, se disminuye sustancialmente el ruido. Para facilitar el ruteo, las pistas de tierra son conectadas a pequeños planos de tierra individuales en la capa superior del circuito, los cuales están conectados al plano de tierra por varias vías.

En orden de minimizar el ruido se utilizó una configuración tipo estrella para las líneas de alimentación. Esto permite separar, por un lado, la fuente de alimentación de los módulos de RF, y por el otro los demás módulos. Capacitores de desacople se agregaron en todos los puntos críticos tan cerca como fue posible del circuito correspondiente. Inductores de RF tipo "chokes" fueron también introducidos para no permitir que el ruido de RF se propagara a otras partes del circuito.


Es esencial minimizar la impedancia de la pista. Para minimizar la resistencia y la inductancia , las pistas deben ser cortas, lo que conlleva a colocar los componentes muy cercanos entre sí. Otros criterios prácticos fueron utilizados: evitar las esquinas de 90º en las pistas, evitar el uso de vías en ruteo de señal así como controlar cuidadosamente los conectores y las soldaduras de forma de garantizar bajas resistencias parásitas.

Consideraciones adicionales

Los efectos de una línea de transmisión de 418MHz deben ser tomados en consideración. Un criterio práctico indica que un modelo de parámetros concentrados puede ser usado si el largo máximo de la pista está por debajo de λ/10. A 418Mhz, esto implica que las pistas deben ser más pequeñas que 7cm, lo que en el diseño fue ampliamente alcanzado, permitiendo diseñar sin tener en consideración efectos de líneas de transmisión.

El layout final de la sección de RF del diseño se muestra en las figuras 4 y 5. El microcontrolador es agregado en una placa separada. Notar que el plano de tierra esta prácticamente ininterrumpido, de modo de no interferir en el camino de retorno de las señales críticas del circuito. El tamaño de la placa es de 64 x 59mms.





PROTOCOLO DE COMNICACIÓN


El protocolo de comunicación debe cumplir con los requerimientos del dispositivo (rango de comunicación, vida de la batería, etc.) y debe también permitir la comunicación entre varios dispositivos remotos y una base fija.

Modos de incrementar la vida de la batería
A continuación se discutirá como el protocolo ayuda a disminuir el consumo, enfocando al caso que un paquete de 10 bytes de data es transmitido desde el remoto a la base cada segundo. Este paquete debe ser contestado con un reconocimiento por la base para asegurar que los datos no fueron perdidos. Entre paquetes el dispositivo se apaga para ahorrar carga de la batería.

Debido al hecho que el consumo de corriente es mucho mayor cuando el dispositivo está transmitiendo o recibiendo datos que cuando el dispositivo esta en modo "sleep", el consumo promedio es prácticamente proporcional al tiempo que el dispositivo está prendido. Los esfuerzos están, entonces, enfocados en reducir este tiempo. Esto puede ser hecho a nivel de protocolo en dos modos básicos.
El primer modo es maximizar la tasa de datos. Esto minimizará el tiempo necesario tanto al transmitir como al recibir los bits requeridos. Un incremento en la tasa de datos, sin embarbo, lleva a una reducción en la sensibilidad del circuito de recepción del transceptor de RF, entonces la distancia máxima de comunicación disminuye. Un valor de compromiso de 60kbps (cercano al valor máximo de 64kbps) es seleccionado. Por sobre ese valor la perdida de performance es importante.


La segunda forma de minimizar el consumo es reducir el overhead en la comunicación, por lo que el tiempo en que el dispositivo está prendido debe ser más pequeño. Directamente relacionado con este tema es el largo del flujo de bits de sincronización que debe ser enviado al comienzo de cada paquete de datos. A pesar que un incremento en el largo de esta trama conlleva una menor tasa de error de bit, se está limitado debido a un incremento en el consumo.

El paquete de datos está compuesto por una trama de sincronización, seguido por una estructura especial para indicar el comienzo de un paquete y por último los datos. La estructura se muestra en la figura 6.


El largo de la trama de sincronización es 16 bits, compuesto por unos y ceros transmitidos alternadamente. Este valor fue ajustado experimentalmente y se encontro que disminuyendo la cantidad de bits lleva a una disminución en la performance.

La estructura de comienzo de paquete ( 12 bits), es la primera parte del paquete y debe ser correctamente recibida para una comunicación adecuada. Se confirmó experimentalmente que decreciendo el largo de esta estructura inicial podría causar la recepción de una importante cantidad de paquetes falsos cuando, con el transmisor apagado, el receptor recibe bits aleatorios debido al ruido.

A pesar que la mejor forma de minimizar el tiempo de comunicación parece en principio que el dispisitivo remoto comience el diálogo (y luego espere un reconocimiento de la base), se encontró que esta aproximación tenía un importante problema. Si un dispositivo remoto comienza la comunicación la base debe estar permanentemente escuchando el canal, esperando un mensaje del dispositivo remoto. Esto causa un corrimiento en la frecuencia en el reloj recuperado, y entonces el tiempo necesario para la sincronización aumenta dramáticamente, incementando, por lo tanto, el consumo.

En el protocolo implementado, la base comienza la comunicación y entonces espera una respuesta del dispositivo remoto que periodicamente se despierta. En el paquete de sincronización está incluido un ID del dispositivo interrogado, entonces solo un sensor responderá y las colisiones se evitan. Luego de la recepción de un paquete de datos la base envía un reconocimiento, y puede interrogar a otro dispositivo.

En la próxima figura se muestra un diagrama simplificado de la comunicación.



El largo de la trama de sincronización es 16 bits, compuesto por unos y ceros transmitidos alternadamente. Este valor fue ajustado experimentalmente y se encontro que disminuyendo la cantidad de bits lleva a una disminución en la performance.

La estructura de comienzo de paquete ( 12 bits), es la primera parte del paquete y debe ser correctamente recibida para una comunicación adecuada. Se confirmó experimentalmente que decreciendo el largo de esta estructura inicial podría causar la recepción de una importante cantidad de paquetes falsos cuando, con el transmisor apagado, el receptor recibe bits aleatorios debido al ruido.


A pesar que la mejor forma de minimizar el tiempo de comunicación parece en principio que el dispisitivo remoto comience el diálogo (y luego espere un reconocimiento de la base), se encontró que esta aproximación tenía un importante problema. Si un dispositivo remoto comienza la comunicación la base debe estar permanentemente escuchando el canal, esperando un mensaje del dispositivo remoto. Esto causa un corrimiento en la frecuencia en el reloj recuperado, y entonces el tiempo necesario para la sincronización aumenta dramáticamente, incementando, por lo tanto, el consumo.

En el protocolo implementado, la base comienza la comunicación y entonces espera una respuesta del dispositivo remoto que periodicamente se despierta. En el paquete de sincronización está incluido un ID del dispositivo interrogado, entonces solo un sensor responderá y las colisiones se evitan. Luego de la recepción de un paquete de datos la base envía un reconocimiento, y puede interrogar a otro dispositivo.

En la próxima figura se muestra un diagrama simplificado de la comunicación.


RESULTADOS EXPERIMENTALES
Las características principales del sistema de prototipo estan sumariadas en las figuras 8 y 9. Estos valores corresponden a una aplicación típica (batería de 2.8V, dispositivo remoto transmitiendo 10 bytes por segundo a una tasa de 60kbps). Como puede verse en la figura 8, el rango de comunicación es mayor que lo inicialmente especificado, aún con la mínima potencia transmitida (-15dBm). Para medir el rango de comunicación se consideró tener una tasa de error de bit menor a 10-4. El consumo de corriente promedio también cumplió completamente con los requerimientos. Para una batería de 1000mAh, la duración se estimó a 1.7 años a máxima potencia, y a 2.6 años a mínima potencia. Los requerimientos para una velocidad relativa entre base y dispositivo remoto son también mejores que las especificadas (más de 2.5m/seg. sin cambio de performance).


Jorge Polentino
CRF
http://iie.fing.edu.uy/investigacion/grupos/microele/papers/jeica04_rf.pdf